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Pull requests: VUnit/vunit

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Pull requests list

Added initial support for external package addition.
#1166 opened Feb 17, 2026 by LarsAsplund Loading…
update build system
#1162 opened Feb 10, 2026 by nbdy Loading…
3
change _create_modelsim_ini() and add ini_flag="ini" for questsim>=ve…
#1134 opened Oct 4, 2025 by asicnet Loading…
Add support for non-byte tdata widths in AXI stream VCs.
#1128 opened Aug 4, 2025 by LarsAsplund Loading…
CI: Do not run scheduled jobs on forks
#1117 opened May 29, 2025 by oscargus Loading…
CI: Use hashes for GitHub Action versions
#1116 opened May 29, 2025 by oscargus Loading…
Add --waves argument to generate waveforms for GHDL and NVC
#1101 opened Mar 5, 2025 by oscargus Loading…
1
3
Add Vivado Block Design support for simulation
#1086 opened Dec 18, 2024 by SzymonHitachi Loading…
1
2
Add APB verification components
#1070 opened Oct 26, 2024 by c-thaler Loading…
8
Fix use reference parsing of instantiated packages
#1056 opened Sep 9, 2024 by diedricm Loading…
Fix link to ghdl docker
#1047 opened Aug 2, 2024 by oscargus Loading…
Add SPI verification components
#1041 opened Jul 11, 2024 by n8tlarsen Loading…
3
modelsim ini options for GUI mode
#1024 opened May 31, 2024 by alexrayne Loading…
2
allow use modelsim predefined external libs
#1023 opened May 31, 2024 by alexrayne Loading…
Add axi master
#1017 opened May 13, 2024 by DavidMartinPhios Loading…
25
Remove redundant directory from Riviera-PRO dataset path Enhancement Tool: RivieraPro
#995 opened Mar 6, 2024 by por3bski Loading… v5.0.0
2
Fix regex for VHDL component instantiations
#990 opened Feb 29, 2024 by javValverde Loading… v5.0.0
2
VHDL-embedded Python code
#986 opened Jan 16, 2024 by LarsAsplund • Draft
17
fix dependency for vhdl instances inside (Sysytem) verilog modules
#979 opened Nov 24, 2023 by roynil Loading…
sim_if/modelsim: use vmap to find modelsim.ini
#975 opened Nov 7, 2023 by bjornfor Loading…
5
Added/Fixed Typing for all files in vunit.ui package Enhancement
#961 opened Sep 28, 2023 by g0t00 Loading… v5.0.0
10
Fix issues when trying to parameterize Verilog modules
#945 opened Jul 12, 2023 by piotrva Loading…
1
11
Move project metadata to pyproject.toml Enhancement
#942 opened Jul 7, 2023 by lavovaLampa Loading… v5.1.0
7
Add type hints to 'parsing/' package Enhancement Parsing
#939 opened May 27, 2023 by lavovaLampa Loading…
5
Unaligned addresses with axi_read_slave
#936 opened May 16, 2023 by crdavis12 Loading…
3
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